The present invention relates to a controller for Cathode Ray Tubes and, more particularly, to a controller which allows transparent addressing of the refresh RAM.
In operating a CRT (Cathode Ray Tube), the codes of the characters to be projected by the electron beam onto the CRT screen are typically stored in a RAM memory. Since the characters projected on the screen by the electron beam decay with time, the CRT controller must periodically take each of the characters out of the RAM memory and use them to control the electron beam for reprojecting the characters onto the screen. This operation is known as refresh, i.e. refreshing the screen display. Each character or portion thereof is thus put on the screen as the electron beam travels across each individual line of the screen.
Additionally, because the information stored in the RAM to be projected on the screen must be periodically changed as conditions change, the information stored in the RAM must be updated. Updating is accomplished by addressing the memory locations of the RAM and inserting the new data into those memory locations. The memory must be updated as often as new data is generated.
Thus, not only must the RAM be addressed for refreshing the screen display but it must also be addressed for updating the stored information.
A primary function of the CRT controller is to constantly retrieve characters from the RAM and to control the video generation circuit of the CRT to display these characters so that the screen display stays active. Therefore, the CRT controller must have access to the RAM. A difficulty arises, however, since the microprocessor or other computer to which the controller is connected must also have access to the RAM for update. The prior art solved the problems of this dual addressing requirement by the use of a memory contention circuit. The typical memory contention circuit of prior CRT controller arrangements comprised an address multiplexer which could receive an address from either the CRT controller or the microprocessing unit. The address multiplexer, of course, required control circuitry so that it could be switched between the microprocessor and the CRT controller. Moreover, this type of system also required transceivers between the control arrangement and the data bus so that the characters to be read into or out of the RAM could be held and then read or written. The use of a memory contention circuit requires the microprocessor to provide the update address during the update operation placing a further burden on the microprocessor operation.
The present invention eliminates the memory contention circuit, i.e. the external multiplexer required to multiplex between the update address supplied by the microprocessor and the refresh address supplied by the CRT controller together with the associated control circuitry for the multiplexer and the transceivers for receiving data between the microprocessor and the RAM, and also relieves the microprocessor of the burden of providing the update addresses for the RAM. Instead, an update address register is provided in the CRT controller to thus provide the update addresses to the RAM so that data can be transferred from the microprocessor to the RAM directly without requiring the microprocessor to additionally address the RAM memory locations. In this type of operation, the RAM appears as a port to the microprocessor instead of a block of memory which must be addressed. As a result, the present invention provides truly transparent addressing of the refresh RAM.